Recently, by using a ferroelectric material in the capacitor of memory cell, a ferroelectric memory device realizing nonvolatility of stored data is devised. The ferroelectric capacitor has a hysteresis characteristic, and if the electric field is zero, a residual polarization of different polarity depending on the hysteresis is left over. By expressing the stored data by the residual polarization of the ferroelectric capacitor, a nonvolatile memory device is realized. The specification of U.S. Pat. No. 4,873,664 discloses two types of ferroelectric memory device.
In a first type, a memory cell is composed of one transistor and one capacitor per bit (1T1C), and a ferroelectric capacitor for reference memory cell is provided in, for example, every 256 ferroelectric capacitors for main body memory cells (normal cells).
In a second type, without using ferroelectric capacitor for reference memory cell, a memory cell is composed of two transistors and two capacitors per bit (2T2C), in which a pair of complementary data are stored in a pair of ferroelectric capacitors for main body memory cell.
For a larger memory capacity, the 1T1C type is advantageous, and at this time, for low voltage operation and operation for a longer life, the design of ferroelectric capacitor for reference cell is important in the ferroelectric cell capacitor for main body memory cell.
As the ferroelectric material for composing capacitor, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3 are known among others. According to PCT International Disclosure No. WO93/12542 Publication, ferroelectric materials extremely small in fatigue as compared with PbTiO.sub.3 --PbZrO.sub.3 suited to ferroelectric memory device are also known.
The constitution of conventional ferroelectric memory device of 1T1C type is described briefly below.
FIG. 7 is a memory cell block diagram, FIG. 8 is a sense amplifier circuit diagram, and FIG. 9 is an operation timing chart.
In FIG. 7, C00 to C37 refer to ferroelectric capacitors for main body memory cells, CD00 to CD31 are ferroelectric capacitors for reference memory cells, CPD is a cell plate driver, and REW0 and REW1 are reference memory cell rewrite signal lines. In addition, SA0 to SA3 are sense amplifiers, and CP is a cell plate signal. And WL0 to WL7 are word lines, RWL0 and RWL1 are reference word lines, and BL0 to BL3, /BL0 to /BL3 are bit lines. In FIG. 8 and FIG. 9, BP is a bit line precharge signal, and /SAP, SAN are sense amplifier control signals. Besides, VSS is a grounding voltage, and VDD is a supply voltage.
In the memory cell composition, for example as shown in the diagrams, bit lines BL0 and /BL0 are connected to the sense amplifier SA0. Further, a ferroelectric capacitor for main body memory cell C00 is connected to the bit line BL0 through an N-channel MOS transistor Tr1 having word line WL0 as its gate. To the bit line /BL0, moreover, a ferroelectric capacitor for reference memory cell CD00 is connected through an N-channel MOS transistor Tr2 having reference word line RWL0 as its gate. The ferroelectric capacitors C00, CD00 are connected to the cell plate signal line CP which is driven by the cell plate driver CPD.
The bit lines /BL0 and /BL1 are connected through an N-channel MOS transistor Tr3 having the reference word line RWL0 as its gate. The bit line BL0 and ferroelectric capacitor for reference memory cell CD00 are connected through an N-channel MOS transistor Tr5 having the reference memory cell rewrite signal line REW0 as its gate.
As shown in FIG. 8, the sense amplifier SA0 is controlled by sense amplifier control signals /SAP, SAN, and the circuit is thus composed so that precharge of bit lines BL0 and /BL0 is controlled by the bit line precharge signal BP.
In this conventional ferroelectric memory device in 1T1C composition is based on a method of using two ferroelectric capacitors of nearly same size as the ferroelectric capacitor for main body memory cell, reading out one H (high) data and one L (low) data, and averaging these two data (see Japanese Laid-open Patent No. 7-262768).
The operation of this conventional ferroelectric memory device of 1T1C composition is described by referring to FIG. 9, mainly relating to selection of word line WL0.
First, the bit lines BL0 and /BL0 are precharged to logic voltage L when the bit line precharge signal BP is H. Similarly, the bit lines BL1 and /BL1 are precharged to logic voltage L.
Consequently, when the bit line precharge signal BP is set to logic voltage L, the bit lines BL0 and /BL0, and the bit lines BL1 and /BL1 are set in floating state.
Next, the word line WL0 and reference word line RWL0 are set in logic voltage H, and the cell plate signal line CP is set to logic voltage H. Herein, the potential level of logic voltage H of the word line WL0 is a voltage boosted over the supply voltage VDD. Since the reference word line RWL0 is set to logic voltage H, the N-channel MOS transistors Tr2 to Tr4 are turned on. In this description, as mentioned above, for example, when the word line WL0 is set to logic voltage H, it means that the potential of the word line WL0 is set to logic voltage H.
At this time, an electric field is applied to both electrodes of the ferroelectric capacitors C00, CD00, C10, CD10 individually, and each potential is determined by the capacity ratio of the ferroelectric capacitor and bit line capacity. Their potentials are read out from the individual bit lines BL0, /BL0, BL1, /BL1.
At this time, the data being read out from the ferroelectric capacitor for reference memory cells CD00 and CD10 are averaged data (potential) of the two data because the N-channel MOS transistors Tr2 to Tr4 are turned on and hence the bit lines /BL0 and /BL1 are connected electrically. Herein, H (high) data is recorded in the ferroelectric capacitor for reference memory cells CD00 and CD01, and L (low) in the ferroelectric capacitor for reference memory cells CD10 and CD11.
Then, setting the reference word line RWL0 to logic voltage L, and turning off the N-channel MOS transistors Tr2 to Tr4, the bit line /BL0 and bit line BL1 are electrically disconnected.
Consequently, the sense amplifier control signal /SAP is set to logic voltage L and the SAN to logic voltage H, the sense amplifier is operated.
As a result, the potential being read out to the bit line is amplified to the supply voltage VDD and grounding voltage VSS.
The reference memory cell rewrite signal line REW0 is set to logic voltage H, so that it is now ready to write the potentials of H (high) and L (low) for next reading operation, in the ferroelectric capacitors for reference memory cells CD00 and CD10.
As the rewriting operation, consequently, the cell plate signal CP is set to logic voltage L. Afterwards, the bit line precharge signal BP is set to logic voltage H and the bit lines BL0 and /BL0 are precharged to logic voltage L, and the word line WL0 and reference word line RWL0 are set to logic voltage L, to be set in initial state.
In this way, in the conventional ferroelectric memory device of 1T1C type, when the word line WL0 is selected, the reference potential used when reading out the potentials of the bit line BL0 and bit line BL1 is the average of the ferroelectric capacitor for reference memory cells CD00 and CD10. The average value is read out from the bit lines /BL0 and /BL1. The reference potential used when reading out the potentials of the bit line BL2 and bit line BL3 is the average of the ferroelectric capacitor for reference memory cells CD20 and CD30. The average value is read out from the bit lines /BL0 and /BL1.
Incidentally, when the word line WL1 is selected, the role of the bit line pair is reversed, and the ferroelectric capacitors for reference memory cells are also different.
That is, the reference potential used when reading out the potentials of the bit line /BL0 and bit line /BL1 is the average of the ferroelectric capacitor for reference memory cells CD01 and CD11. The average value is read out from the bit lines BL0 and BL1. The reference potential used when reading out the potentials of the bit line /BL2 and bit line /BL3 is the average of the ferroelectric capacitor for reference memory cells CD21 and CD31. The average value is read out from the bit lines BL0 and BL1.
Therefore, in the constitution shown in FIG. 7, for eight word lines WL0 to WL7, there are four types of reference potential.
However, the reference memory cell system of the conventional ferroelectric memory cell device of 1T1C type had the following problems.
That is, hitherto, two ferroelectric capacitors for reference memory cells in which H (high) and L (low) data are written individually (for example, ferroelectric capacitors for reference memory cells CD00 and CD10) were electrically connected, both potentials were averaged, and the average was used as the reference potential for reading out the data. As a result, due to fluctuations of these ferroelectric capacitors for reference memory cells, the reference potentials were varied. As a result, the ideal reference potential which should be always the same value was not always obtained, and the yield of the ferroelectric memory device was lowered.
In particular, such fluctuations of ferroelectric capacitors for reference memory cells were closely related to the layout configuration, and if the configuration of the ferroelectric capacitors for reference memory cells and the ferroelectric capacitors for main body memory cells was remote from each other, an ideal reference potential could not be obtained.
Moreover, in the reference memory cell system of the conventional ferroelectric memory cell device of 1T1C type, the N-channel type MOS transistors and ferroelectric capacitors for reference memory cells as control signals and control switch elements were required in each bit line, which occupied a wide area in layout.